Field of the Invention
The present invention relates to a circuit board including a plurality of terminals to which an electronic component, such as an integrated circuit (IC) chip, is connected by flip-chip bonding.
Description of the Related Art
Semiconductor integrated circuit devices (IC chips) used as microprocessors of computers or the like generally include many external connection terminals on the bottom surface thereof. In particular, IC chips having many signal terminals arranged along the outer periphery of the bottom surface thereof are called peripheral-type IC chips. Terminals to which the terminals on the IC chips are to be connected by flip-chip bonding are provided on a principal surface of a circuit board on which the IC chips are to be mounted. In recent years, with the increase in the terminal density of the IC chips, the number of terminals on the circuit board has been increased and the terminal pitch has been reduced.
Japanese Unexamined Patent Application Publication No. 2011-14644 discloses an example of a circuit board to which a peripheral-type IC chip can be connected by flip-chip bonding. This circuit board has a chip mounting region on a principal surface thereof, the chip mounting region having a rectangular shape that corresponds to the external shape of the IC chip. A plurality of signal terminals are arranged along the outer periphery of the chip mounting region. The signal terminals are provided on portions of band-shaped wiring conductors. The wiring conductors are covered with a solder resist layer that is provided on the principal surface of the board as an outermost resin insulating layer, so that most part of each wiring conductor is not exposed. The signal terminals are exposed at the same opening formed in the solder resist layer. In other words, the signal terminals have a non-solder mask defined (NSMD) structure. The exposed terminals and terminals on the IC chip (for example, terminals having a copper pillar structure) are arranged so as to face each other, and are electrically connected to each other with solder bumps or the like provided therebetween.
If the pitch of the signal terminals arranged in the same opening formed in the solder resist layer is small, there is a risk that solder will flow between the adjacent terminals and the terminals will be short-circuited. In addition, when only the lower surfaces of the fine signal terminals are bonded to the underlying resin insulating layer, there is a risk that the bonding strength will be insufficient. Accordingly, Japanese Unexamined Patent Application Publication No. 2013-239603, for example, proposes a structure in which insulating reinforcing portions are provided between the signal terminals in the opening. This circuit board is structured such that the lower surfaces and portions of side surfaces of signal terminals are supported by reinforcing portions that define the inner bottom surface of the opening. With this structure, the risk of short-circuiting between the terminals is reduced and the bonding strength of the terminals is increased. In addition, formation of voids in an underfill that fills the space between the IC chip and the circuit board can be suppressed.
The above-described circuit boards according to the related art generally include power supply terminals and ground terminals arranged in a central area of the chip mounting region in addition to the signal terminals arranged at the outer periphery of the chip mounting region. If these terminals are all provided with the above-described reinforcing portions, the following problem occurs when the terminals on the circuit board are connected to the terminals on the IC chip by soldering. That is, the areas of portions of the surfaces of the power supply terminals and ground terminals, the portions being connected to the solder, are reduced, and the solder cannot reliably flow to the side surfaces of the terminals on the circuit board. Therefore, there is a risk that the connection areas between the solder and the power supply terminals and between the solder and the ground terminals will be insufficient and the efficiency of power supply to the IC chip will be reduced. As a result, there is a possibility that the IC chip cannot reach its full performance potential.